The present invention relates to a semiconductor memory device.
In recent years, the tendency has been to form semiconductor memory devices (hereinafter referred to simply as "memories") with higher densities. As a result, a so-called 256K structure memory (random access memory (RAM) has come into practical use, wherein memory constructions of "256K word.times.1 bit" and "256K word.times.4 bit" are employed. The former memory construction features a one-block memory, and the latter memory construction features a four-block memory. Therefore, the latter type of memory produces so-called multibit outputs.
Such large capacity memories as mentioned above can neither be manufactured nor tested easily, since many steps are required for the performance test. In addition, it has becomes more complicated to test recent memories for performance, since the recent trend is to mount not only a memory but also various logic circuits on a single chip together with the memory at its periphery.
Under such circumstances, there is the problem that it is not easy to find short-circuits between bit lines in the memories, as between one block and another adjacent block, during a performance test. If such short-circuits of the bit lines are not found and are left as they are, they will cause write errors during usual write operations and/or read errors during usual read operations.